The present invention relates to a semiconductor memory device and, more particularly, to an improvement in a dynamic random access memory device having a dual word line structure including main-word and sub-word lines.
As well known in the art, a semiconductor memory device having a plurality of word lines, one of which is selected and energized to an active level. In accordance with an increase in memory capacity, each of the word lines is inevitably prolonged to have a relatively large stray resistance. The word line is thereby required to be made of a metal to reduce its resistance. In accordance also with increase in memory capacity, a pitch for the word line is reduced. This means that the pitch for metal wiring is considerably made small, so that the increase in memory capacity is restricted. In other words, it is difficult to construct a memory device having a large memory capacity such as 64-Mb or 256-Mb with a conventional word line structure.
Therefore, such a memory device having a dual word line structure was proposed in "1992 SYMPOSIUM ON VLSI CIRCUITS", Digest of Technical Papers, pp. 112-113, entitled "A Boosted Dual Word-line Decoding Scheme for 256 Mb DRAMs". The memory device proposed therein has a plurality of main-word lines each made of a metal and a plurality of sub-word lines each made of polysilicon and serving also as gates of memory transistors connected thereto. One of the main-word lines is selected and driven by a row decoder in response to a part of row address signals. Each of the sub-word lines is connected to an output node of an associated one of sub-word drivers each further including an input node connected to an associated main-word line and a power node. The sub-word drivers arranged in the same column are connected at the power nodes thereof in common to an associated one of word drive decoders. Each of the word drive decoders responding to another part of row address signals to output and supply an energizing voltage to the power nodes of associated ones of the sub-word drivers. Accordingly, the sub-word driver drives the associated sub-word line to an active level in response to a selection level of the associated main-word line and to the energizing voltage from the associated word drive decoder.
With a such construction, the pitch for metal wiring as the main-word line is widened, so that each memory cell size is made small and a great number of memory cells are formed between the adjacent main-word lines. Accordingly, a memory device having a lager memory capacity such as 64-Mb or 256-Mb can be constructed without increase in chip area.
In the memory device as described above, however, the sub-word drivers arranged in the same column are connected in common to the associated word drive decoder. That is, each word drive decoder has a remarkably large stray capacitance and is required to charge and discharge such a large capacitance in each data reading or writing cycle. The power consumption is thus made large and an operation speed is lowered.